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Advanced
FPGA and SOPC Development, Experiment |
Teaching System |
FD-FPGA & SOPC_SYS |
Download:
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| Overview |
|  Advanced
FPGA and SOPC development, experiment and teaching system, FD-FPGA&SOPC_SY,
functions not only as an advanced development, experiment and teaching
system for digital circuit and digital systems, but also as an advanced
design, development, experiment and teaching one for SOPC(System
On Programming Chip), as well as an ideal IP core design, development,
verifying experiment and teaching one. The hardware platform of
this system can be employed for design and development of advanced
FPGA digital system and advanced SOPC, and for development verification
of medium- and small scaled IP design.
FD-FPGA&SOPC_SYS incorporates ample hardware, taking one million
lines ALTERA CYCLONE series FPGA EP1C20 as the core unit with EPCS4
chip of 4Mbit memory, 1MByte SRAM, 16MByte SDRAM, and 16MBit FLASH.
Various functional interfaces include: two RS23 com, USB 2.0, two
PS/2 mouse and keyboard interfaces, I2C and 8 colors VGA, 4X4 small
keyboard, on-off input, beeper output, LCD interface and 2X32 LCD
Module, digital display, 8 indicator lights etc., as well as 1 line
video input/ 1 line output interface. Extension interface is also
available.
The software of FD-FPGA&SOPC_SYS is equipped with development
and simulation instruments for all digital circuit, digital system
and SOPC:
1. Altera Quartus II 5.0 : the up-to-date FPGA and PLD development
instrument for digital circuit, digital system;
2. Nios Ⅱ Development Kit 5.0(SOPC Buider): the up-to-date development
instrument for embedded SOPC;
3. ModelSim ： the ideal simulation instrument for embedded digital
systems.
FD-FPGA&SOPC_SYS provides plentiful technical documents and
teaching information: detailed manual, instructions for digital
circuit/system design, development and experiment, instructions
for SOPC design, development and experiment, instructions for IP
core design, development and experiment. In addition, reference
designs and codes are furnished for all experiments.
FD-FPGA&SOPC_SY application：teaching and experiment for
FPGA at universities, development, design, teaching and experiment
for SOPC at universities, circuit design at universities or IC design
lab, leaning and experiment platform for advanced FPGA, leaning
and experiment platform for SOPC, leaning and experiment platform
circuit / IC design, prototype verifying platform for product development,
verifying platform for IC front-end IC design, and training platform
for digital system/SOPC development and IC design.
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| Highlights |
◆ one million lines ALTERA
CYCLONE series FPGA EP1C20 as the core unit
◆ EPCS4 chip of 4Mbit memory
◆ 1MByte SRAM
◆ 16MByte SDRAM
◆ 16MBit FLASH
◆ 2 RS23 com
◆ USB 2.0
◆ 2 PS/2 mouse and keyboard interfaces
◆ I2C interface
◆ VGA interface
◆ 4X4 keyboard
◆ on-off input
◆ beeper output
◆ LCD interface and LCD Module
◆ 4 digits digital display
◆ 8 indicator lights output
◆ 1 line video input/ 1 line output interface
◆ Extension interface
◆ plentiful documents: detailed manual, instructions for hardware
design, instructions for digital system design, development and
experiment, instructions for SOPC design, development and experiment,
instructions for IP core design, development and experiment. In
addition, reference designs and codes are furnished for all experiments.
◆ Reference designs and codes for all experiments.
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| Specifications |
| Hardware Components |
Items |
Description |
| core |
| one million lines ALTERA CYCLONE series
FPGA EP1C20 |
| EPCS4 chip of 4Mbit memory |
|
| Memory |
| -1MByte SRAM |
| -16MByte SDRAM |
| -16MBit FLASH |
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| Serial interface |
2 standard RS 232 I/O |
| USB |
One USB2.0 |
| PS/2 |
1 PS/2 mouse and 1 PS/2 keyboard I/O |
| VGA interface |
VGA |
| I2C |
I2C interface |
| Display |
LCD interface and LCD module |
| input |
| - 4 X 4 small keyboard |
| - on-off input |
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| output |
| - 4digits display |
| - 8 indictor lights |
| - beeper |
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| video |
| - 1line video input |
| - 1line video output |
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| extension |
Extension interface |
| JTAG download |
1 JTAG download interface |
| AS download |
1 AS download interface |
| Download tool |
JTAG/AS download/debugging tool |
| Cable |
－ RS232 Cable
－ JTAG Cable |
| AC adapter |
One 5V adapter |
| Mechanical |
350mm x 230mm x 110mm |
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| Software Components |
Items |
Description |
| Digital system |
Altera Quartus II 5.0 : the up-to-date FPGA and
PLD development instrument for digital circuit, digital system |
| SOPC |
Nios Ⅱ Development Kit 5.0(SOPC Buider): he up-to-date
development instrument for embedded SOPC |
| IP simulation |
ModelSim ： the ideal simulation instrument for
embedded digital systems |
| Experiment of advanced FPGA&SOPC system |
Part I Basic experiments
of digital system designing and reference designs and codes
Part II experiments of digital system interface designing
and reference designs and codes
Part III experiments of comprehensive designing of digital
systems and reference designs and codes
Part IV experiments of SOPC system designing and reference
designs and codes
Part V experiments of IP core designing and reference designs
and codes |
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| Documents |
Items |
Description |
1 |
Design principle chart of hardware systems |
2 |
Detailed manual, Instructions for hardware design |
3 |
Instructions Book for digital circuit/system design,
development and experiment |
4 |
Instructions Book for SOPC design, development
and experiment |
5 |
Instructions Book for IP core design, development
and experiment |
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| Application |
◆ Teaching and experiment
for digital system FPGA at universities
◆ Development, design, teaching and experiment for SOPC at universities
◆ Digital Circuit design & development at universities lab or
IC design lab
◆ Leaning and experiment platform for advanced FPGA
◆ Leaning and experiment platform for SOPC
◆ Prototype verifying platform for product development
◆ Verifying platform for IC front-end IC design & verification
◆ Training platform for digital system/SOPC development and IC design
& verification |
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| Order Information |
| Order Number |
Description |
| FD-FPGA&SOPC_SYS |
-- Design,Development & Teaching experiment
system for advanced digital system FPGA & SOPC
-- Learning and
experiment system for advanced FPGA & SOPC design & development
-- IP design & verification platform |
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Download:
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Content and Index
of Technical Documents & Textbooks:
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| Contents and Index
of Instruction of Advanced FPGA & SOPC Design, Development& Experiment: |
The book falls into
four parts. Part I details the designing of digital systems
and complete experiment guidance, beginning with explaining
the use of digital system design software QuartusII. Then
following three divisions present the design experiments of
digital systems: basic experiments, interface design experiments
and comprehensive design. Part II expounds the design experiment
of IP core. Part III describes the use and design experiment
of SOPC software NiosII. Part IV is the appendix, demonstrating
the installation process of digital system and SIPC design
simulation software, operating diagrams of NiosII SOPC Builder
and manual of simulation software Modlesim.
This book functions as the complementary textbook for Advanced
FPGA and SOPC development, experiment and teaching system,
FD-FPGA&SOPC_SY developed by Fudan Tech. It incorporates
affluent and valuable contents with state-of-the-art technology,
with strong practicability. The book can be the experimental
textbook for electronic information department of higher education
institutions, or technical information for engineers specialized
in embedded system design.
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PART I DESIGN AND
EXPERIMENT OF DIGITAL SYSTEM
CHAPTER 1 THE USE AND GUIDANCE OF DESIGN SOFTWARE QUATUSII
5.0O
DIGITAL SYSTEM ......P12
1. OVERVIEW ......P12
2. DESIGNING PROCESS OF QUATUSII ......P14
3. ESTABLISHING PROJECT ......P14
4. ESTABLISHING DESIGN ......P15
4.1 USING QUATUSII BLOCK EDITOR TO SET UP THE FILE OF PRICIPLE
DIANGRAMS ......P17
4.2 USING QUARTUS II TEXT EDITOR ......P17
4.3 USING VERILOG HDL,VHDL AND AHDL ......P18
5. COMPILIING COMPREHENSIVE DESIGN ......P18
6. SIMULATING PROJECT ......P20
7. DISTRIBUTING EQUIPMENT AND PINS ......P22
8. DOWNLOADING PROGRAMS ......P25
１.Downloading by jtag ......P25
２. Downloading byＡＳ（FPGA burning ） ......P28
9. DEBUGGING AND THE USE OF SOFTWARE LOGIC ANALYSER ......P29
10. SETTING TRGGERS ......P30
CHAPTER 2 EXPERIMENTS OF DIGITAL CIRCUIT AND DIGITAL SYSTEM
DIVISION ONE BASIC EXPERIMENTS OF DIGITAL SYSTEM ......P31
EXPERIMENT 1 3/8 DECODER ......P31
1. Purpose ......P31
2. Principle and explanations ......P31
3. experiment details and requirements ......P32
4. Steps ......P32
5. Requirements for summary report ......P32
6. Reference design and examples ......P33
Questions ......P33
EXPERIMENT 2 FREQUENCY DEVIDER ......P34
1. Purpose ......P34
2. Principle and explanations ......P34
3. Experiment details and requirements ......P34
4. Steps ......P34
5. Requirements for experiment report ......P35
6. extension experiment ......P35
7. Reference design and examples ......P35
EXPERIMENT 3 LPM CORE BASED SINE FUNCTION GENERATOR ......P37
Preparation ......P37
1. Purpose ......P37
2. Principle and explanations ......P37
3. Experiment details and requirements ......P46
4. Steps ......P47
5. Requirements for summary report ......P47
6. extension experiment ......P47
7. Reference design and examples ......P48
EXPERIMENT 4 EXPERIMENT OF DECODER WITH BCD 7-SEGMENT DISPLAY ......P50
Preparation ......P50
1. Purpose ......P50
2. Principle and explanations ......P50
3. Experiment details and requirements ......P52
4. Steps ......P52
5. Requirements for experiment report ......P52
6. extension experiment ......P52
7. Reference design and examples ......P52
EXPERIMENT 5 SCANNING DIGITAL DISPLAY ......P55
Preparation ......P55
1. Purpose ......P55
2. Principle and explanations ......P55
3. Experiment details and requirements ......P56
4. Steps ......P57
5. Requirements for summary report ......P57
6. Reference design and examples ......P57
EXPERIMENT 6 FREQUENCY METER ......P59
Preparation ......P59
1. Purpose ......P59
2. Principle and explanations ......P59
3. Experiment details and requirements ......P60
4. Steps ......P60
5. Requirements for summary report ......P60
6. Reference design and examples ......P61
EXPERIMENT 7 USE OF SCANNING KEYBOARD ......P67
Preparation ......P67
1. Purpose ......P67
2. Principle and explanations ......P67
3. Experiment details and requirements ......P67
4. Steps ......P68
5. Requirements for summary report ......P68
6. Extension study ......P68
7. Reference design and examples ......P69
EXPERIMENT 8 UTILITY MULIFUNCTIONAL E-METER ......P77
Preparation ......P77
1. Purpose ......P77
2. Experimental contents ......P77
3. Experiment details and requirements ......P79
4. Steps ......P79
5. Requirements for summary report ......P79
F Reference design and examples ......P80
DIVISION 2 INTERFACE DESIGN EXPERIMENTS OF DIGITAL SYSTEM ......P91
EXPERIMENT 9 EXPERIMENT OF LCD DISPLAYING ......P91
Preparation and thingking over ......P91
1. Purpose ......P91
2. Principle and explanations ......P91
3. Tips ......P92
4. Steps ......P92
5. Experiment details and requirements ......P92
6. Requirements for summary report ......P93
7. Thinking over ......P93
8. Reference design and examples ......P93
EXPERIMENT 10 RS-232 SERIAL CONTROLLER ......P108
Preparation and thingking over ......P108
1. Purpose ......P108
2. Principle and explanations ......P108
3. Tips ......P110
4. Steps ......P110
5. Experiment details and requirements ......P110
6. Requirements for summary report ......P110
7. Reference design and example ......P111
EXPERIMETN 11 OUTPUT EXPERIMENT OF VGA CONTROL ......P113
Preparation and thingking over ......P113
1. Purpose 113
2. Principle and explanations ......P113
3. Steps ......P113
5. Experiment details and requirements ......P113
6. Requirements for experiment report ......P114
7. Reference design and example ......P114
EXPERIMENT 12 EXPERIMENT OF PS/2 KEYBOARD CONTROLLER ......P121
Preparation and thingking over ......P121
1. Purpose ......P121
2. Principle and explanations ......P121
3. Steps ......P121
4. Experiment details and requirements ......P122
5. Requirements for experiment report ......P122
6. Thinking over ......P122
7. Reference design and example ......P122
APP：ASCII lookup ......P123
EXPERIMENT 13 EXPERIMENT OF INTERFACE INTERCONNECTION ......P141
1. Purpose ......P141
2. Principle and explanations ......P141
3. Tips ......P141
4. Steps ......P141
5. Experiment details and requirements ......P142
6. Requirements for experiment report ......P142
7. Reference design and example ......P142
DIVISION THREE EXPERIMENT OF COMPREHENSIVE DESIGN ......P143
EXPERIEMENT 14 EXPERIMENT OF COMPREHENSIVE DESIGN ......P143
1. Purpose ......P143
2. Principle and explanations ......P143
3. Tips ......P143
4. Steps ......P143
5. Experiment details and requirements ......P144
6. Requirements for summary report ......P144
7. extension study ......P144
8. Reference design and example ......P145
PART II DESIGN EXPERIMENT OF IP CORE DESIGN
CHAPTER 3 DESIGN EXPERIMENT OF IP CORE ......P148
DIVISION 4 DESIGN EXPERIMENT OF IP CORE ......P148
EXPERIMENT 15 RS-232 SERIAL CONTROLLER ......P148
Preparation ......P148
1. Experimental contents ......P148
2. Principle and explanations ......P148
3. Steps ......P149
4. Experiment details and requirements ......P152
5. Reference design and example ......P152
EXPERIMENT 16 OUTPUT EXPERIMENT OF VGA CONTROL ......P153
Preparation ......P153
1. Experimental contents ......P153
2. Principle and explanations ......P153
3. Steps ......P153
4. Experiment details and requirements ......P153
5. Reference design and example ......P154
EXPERIMENT 17 LOOP DESIGN OF VEDIO INPUT&OUTPUT ......P155
Preparation ......P155
1. Experimental contents ......P155
2. Steps ......P155
3. Experiment requirements ......P159
4. Requirements for summary report ......P160
5. Reference design and example ......P160
EXPERIMENT 18 DESIGN OF YCBCR->RGB CONVERTOR ......P161
1. Principle ......P161
2. Experimental contents ......P163
3. Simulating steps of converting YCbCr to RGB ......P165
4. Requirements ......P168
5. Reference design and example ......P169
EXPERIMENT 19 RS CODING PRINCIPLE AND ERROR CORRECTING ALGEBRA ......P170
1. Principle ......P170
2. Experimental contents ......P175
3. Simulating steps of RS coding module ......P177
4.Requirements ......P179
5. Reference design and example ......P180
EXPERIMENT 20 THE REALIZATION OF SDRAM CONTROLLER ......P181
1. Principles and control methods of SDRAM ......P181
2. Design realization of SDRAM controller ......P182
3. Description of SDRAM controller interface . ......P186
4. Testing methods of SDRAM controller ......P186
5. Simulating steps of SDRAM controller ......P186
6. Requirements ......P191
7. Reference design and examples ......P192
PART III DESIGN AND EXPERIEMENT OF SOPC
CHAPTER 4 USE AND GUIDANCE OF SOPC DESIGN SOFTWARE NIOSII 193
1 INTRODUCTION OF NIOSII ......P193
2 DEVELOPMENT INSTRUMENT OF SOPC BUILDER ......P194
2.1 Introduction of SOPC Builder ......P194
2.2 User view of SOPC Builder ......P195
3 DESIGN PROCESS OF NIOSII ......P197
3.1 The process of hardware development ......P198
3.2 The process of software development ......P199
CHAPTER 5 DESIGN EXPERIMENT OF SOPC ......P200
DIVISION 5 DESIGN EXPERIMENT OF SOPC ......P200
EXPERIMENT 21 EXAMPLE OF NIOS II DEVELOPMENT PROCESS---LED
DISPLAY ......P200
1. Purpose ......P200
2. Principle and explanations ......P200
3. Steps ......P225
4. Experiment details and requirements ......P226
5. Requirements for experiment report ......P226
6. Extension requirements ......P226
EXPERIMENT 22 CONFIGUARATION OF STANDARD NIOS II HARDWARE
SYSTEM ......P227
1. Purpose ......P227
2. Experimental contents ......P227
3. Steps ......P235
4. Requirements for experiment report ......P236
5. Extension study ......P236
F Reference design and examples ......P236
EXPERIMENT 23 REALIZING COMMUNICATION BETWEEN UART— JTAG HOST
AND FPGA ......P237
1. Purpose ......P237
2. Principle and explanations ......P237
3. Steps ......P238
4. Experiment details and requirements ......P238
5. Requirements for experiment report ......P239
EXPERIMENT 24 EXPERIMENT OF SYSTEM ID ......P240
1. Purpose ......P240
2. Principle and explanations ......P240
3. Steps ......P241
4. Experiment details and requirements ......P241
5. Requirements for experiment report ......P241
F Reference design and examples ......P241
EXPERIMENT 25 REALIZING COMMUNICATION OF SERIAL INTERFACES ......P243
1. Purpose ......P243
2. Principle and explanations ......P243
3. Steps ......P244
4. Experiment details and requirements ......P244
5. Requirements for experiment report ......P245
6. Extension experiments ......P245
7. Reference design and examples ......P246
EXPERIMENT 26 REALIZING LCD DISPLAYING ......P249
1. Purpose ......P249
2. Principle and explanations ......P249
3. Steps ......P250
4. Experiment details and requirements ......P250
5. Requirements for experiment report ......P250
6. Extensionexperiments ......P250
7. Reference design and examples ......P251
EXPERIMENT 27 KEY TRIGER AND COUNTER ......P252
1. Purpose ......P252
2. Principle and explanations ......P252
3. Steps ......P253
4. Experiment details and requirements ......P253
5. Requirements for experiment report ......P254
6. Reference design and examples ......P254
EXPERIMENT 28 SIMPLE DIGITAL CLOCK ......P258
1. Purpose ......P258
2. Principle and explanations ......P258
3. Steps ......P259
4. Experiment details and requirements ......P259
5. Requirements for experiment report ......P259
6. Reference design and examples ......P259
EXPERIMENT 29 EXPERIMENT OF FLASH FUNCTION TESTING ......P267
1. Purpose ......P267
2. Principle and explanations ......P267
3. Steps ......P269
4. Experiment details and requirements ......P269
5. Requirements for experiment report ......P269
6. Reference design and examples ......P269
PART ⅣAPPENDIX
APP. 1 INSTALLATION OF DESIGN DEVELOPMENT SOFTWARE ......P280
1. INSTALLATION AND RUNNING OF QUARTUSII5.0 ......P280
2. INSTALLATION OF MODELSIM ......P291
3. INSTALLATION OF O NIOS II IDE ......P294
APP. 2 OPERATION DIAGRAMS OF NIOSII SOPC BUILDER ......P298
1. OPEN QUARATUSII ......P298
2. OPEN SOPCBUILDER ......P299
3. SELECT SYSTEM GENERATION ......P301
4. CLICK RUN NIOSII IDE ......P302
5. COMPILING FILES ......P307
6. DOWNLOADING FIRST HARDWARE PROJECT UNDER QARATUSII INTO
EXPERIMENTAL BOARD ......P308
7. DOWNLOADING SOFTWARE WITH THE EXPERIMENTAL BOARD POWER
ON ......P309
8. HOW TO ESTABLISH NEW SOFTWARE PROJECT ......P311
APP. 3 MANUAL OF MODELSIM ......P321
1. PREFACE ......P321
2. CODE SIMULATION ......P321
2.1 Files required in code simulation ......P321
2.2 Steps of code simulation ......P322
3 GATE-LEVEL SIMULATION AND TIME SERIES SIMULATION ......P325
3.1 Files required in code simulation ......P326
3.2 Steps of code simulation ......P326 |
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| Contents and Index of Guide of Advanced FPGA & SOPC Development
System: |
This Manual is divided
into twelve chapters. Chapter one introduces the functions,
features and applications of advanced FPGA&SOPC design,
development, experiment and teaching system. Chapter two explains
the makeup, structure and linking of the system. Chapter three
describes main parts and their characteristics employed in
the system. Chapter four to twenty one expounds hardware design
principles, configurations and corresponding FPGA pins configuring
of each hardware interface used in the system. The trainees
can understand hardware design principles of the system or
perform the provided experiments by referring to this manual.
This manual serves as the complementary documents of advanced
FPGA&SOPC design, development, experiment and teaching
system FD-FPGA&SOPC_SYS developed by Fudan Tech, expounding
hardware designing principles of the system. The manual can
be the experimental textbook for electronic information department
of higher education institutions, or technical information
for engineers specialized in embedded system design.
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PREFACE ......P2
CHAPTER 1 INTRODUCTION OF THE SYSTEM
1.1 OVERVIEW ......P5
1.2 FEATURES ......P6
1.3 SPECIFICATIONS ......P7
1.3.1 Hardware ......P7
1.3.2 Software ......P8
1.3.3 Documents ......P8
1.4 APPLICABLE AREAS ......P8
1.5 ORDER INFORMATION ......P9
CHAPTER 2 MAKEUP AND STRUCTURE OF THE SYSTEM ......P10
2. 1 SYSTEM MAKEUP ......P10
2.2 MAKEUP OF HARDWARE DEVELOPMENT PLATFORM AND FUNCTION LAYOUT
......P10
2.3 SYSTEM CONNECT ......P13
CHAPTER 3 MAIN COMPONENTS AND THEIR FEATURES ......P15
CHAPTER 4 4-DIGIT 7-SEGMENT DISPLAY ......P18
CHAPTER 5 BEEPER AND DIGITAL TUBE ......P21
CHAPTER 6 VGA INTERFACE ......P23
CHAPTER 7 PS/2 MOUSE∕KEYBOARD INTERFACE ......P27
CHAPTER 8 RS-232 SERIAL INTERFACE ......P32
CHAPTER 9 4X4SCANNING KEYBOARD ......P36
CHAPTER 10 CHARACTER TYPE LCD DISPLAY ......P38
CHAPTER 11 USB INTERFACE AND CHIPS ......P42
CHAPTER 12 VIDEOCOLLECTING/ OUTPUT MODULE ......P44
CHAPTER 13 USER DEFINEDSERAIL INTERFACE AND I2C INTERFACE ......P53
CHAPTER 14HIGH SPEED ASYNCHRONOUS SRAM ......P54
CHAPTER 15 HIGH SPEED SYNCHRONOUS SDRAM ......P57
CHAPTER 16 LARGE VOLUME SWIFT FLASH ......P59
CHAPTER 17EXTENSION BOARD INTERFACE ......P61
CHAPTER 18 JTAGDOWNLOADING AND DEBUGGING INTERFACE ......P62
CHAPTER 19 POWER DISTRIBUTION ......P63
CHAPTER 20 RESET CIRCUIT ......P65
CHAPTER 21 CLOCK POWER SOURCE ......P66
APPENDIX: SYSTEM SCHEMATIC ......P68
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